Department of Electrical and Computer Engineering Seminar — Junseok Chae @ ElectroScience Laboratory, MRC Conference Room #132,
Dec 7 @ 11:00 am – 12:00 pm

Seminar: Wireless Fully-Passive Recording/Stimulation Devices for Neural Engineering

Discussion by Prof. Junseok Chae
Monday, December 7, 2015, 11:00 am

Wireless Fully-Passive Recording / Stimulation Devices for Neural Engineering



Prof. Junseok Chae, School of Electrical, Computer and Energy Engineering, Arizona State University


11:00 AM – 12:00 PM, Monday, December 7th, 2015


ElectroScience Lab, The Ohio State University, MRC Conference Room #132, 1330 Kinnear Road, Columbus, OH 43212


Neural recording / stimulation devices to chronically record / stimulate biosignal, i.e., neuropotentials, in our bodies have been of great interest to scientists due to their potential benefits to diagnosis and treatment. Existing recording / stimulating system all comprise active components such as amplifier and microcontroller. One of the main concerns of using active components is the heat generation from the electronics could lead to heat trauma. Our work overcomes this disadvantage via fully-passive wireless biotelemetry. This unique wireless telemetry utilizes EM backscattering methods to record / stimulate biosignal. Their small size and ability to operate without any battery or energy harvester make them attractive and feasible for chronic recording / stimulation inside or on the body. We, for the first time, demonstrate wireless recorder having sensitivity of less than 60μVpp and stimulator having capability of more than 1 mA, all operating in a fully-passive manner.


Junseok Chae received the B.S. degree in metallurgical engineering from the Korea University, Seoul, Korea, in 1998, and the M.S. and Ph.D. degrees in EECS (Electrical Engineering and Computer Science) from the University of Michigan, Ann Arbor, in 2000 and 2003, respectively. He joined Arizona State University as an assistant professor in electrical engineering in 2005 and now he is an associate professor. His research areas of interest are MEMS for biomedical/bioenergy applications.

He received the 1st place prize and the best paper award in DAC (Design Automation Conference) student design contest in 2001. He has published over 100 journal and conference articles, one book, seven book chapters, and holds three US patents. He serves as a technical program committee member of IEEE MEMS conference and He received NSF (National Science Foundation) CAREER award on MEMS protein sensor array.


Department of Electrical and Computer Engineering Dissertation Defense — Roberto Myers @ 477 Watts Hall
Dec 10 @ 9:30 am – 10:30 am

You are invited to attend the public dissertation defense of ATM Golam Sarwar on Thursday, December 10th at 09:30am in 477 Watts Hall

Dissertation Title “Extreme Band Engineering of III-Nitride Nanowire Heterostructures for Electronic and Photonic Application”

Dissertation Committee:

Professor Roberto Myers,

Advisor Professor Steve Ringle

Professor Siddharth Rajan

Speaker Biography

Sarwar received his Bachelor of Science and Master of Science in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology in 2009 and 2011, respectively. Since Autumn 2011, he is working towards his PhD with Prof. Roberto Myers in the Department Electrical and Computer Engineering of The Ohio State University. His research interest includes physics and application of nano-structures in electronic, optoelectronic and photonic devices especially nanowire LEDs. Abstract Bottom-up nanowires are attractive for realizing semiconductor devices with extreme heterostructures because strain relaxation through the nanowire sidewalls allows the combination of highly lattice mismatched materials without creating dislocations. The resulting nanowires are used to fabricate light-emitting diodes (LEDs), lasers, solar cells, and sensors. The aim of this work is to investigate extreme heterostructures, which are impossible or very hard to realize in conventional planar films, exploiting the strain accommodation property of nanowires and engineer their band structure for novel electronic and photonic applications. To this end, in this thesis, III-Nitride semiconductor nanowires are investigated. In the first part of this work, a complete growth phase diagram of InN nanowires on silicon using plasma assisted molecular beam epitaxy is developed, and structural and optical characteristics are mapped as a function of growth parameters. Next, a novel up-side down pendeoepitaxial growth of InN forming mushroom like microstructures is demonstrated and detail structural and optical characterizations are performed. Based on this, a method to grow strain free large area single crystalline InN or thin film is proposed and the growth of InN on patterned GaN is investigated. The optimized growth conditions developed for InN is further used to grow InGaN nanowires graded over the whole composition range. Numerical energy band simulation is performed to better understand the effect of polarization charge on photo-carrier transport in these extremely graded nanowires. A novel photodetector device with negative differential photocurrent is demonstrated using the graded InGaN nanowires. In the second part of this thesis, polarization induced nanowire light emitting diodes (PINLEDs) are investigated. The electrical and optical properties of the nanowire heterostructure are engineered and optimized for ultraviolet and deep ultraviolet applications. The electrical efficiency of the devices is engineered by either aggressively grading the p-type base or by intergrading a polarization induced tunnel junction at the base. The active region of the LEDs is tailored to have efficient emission at deep ultraviolet wavelengths by either extreme quantum confinement or by softening the potential profile of the quantum wells. Finally, the growth of III-N nanowires on metal substrates is demonstrated for cheap and scalable nanowire device applications.


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Department of Electrical and Computer Engineering Meet Up – Betty Lise Anderson @ ElectroScience Laboratory
Jan 14 @ 6:00 pm – 7:00 pm

MeetUp: Engineering Outreach

Alumni build outreach projects and learn how to get involved
Thursday, January 14, 2016, 6:00 pm

Betty Lise Anderson, program administratorSave the date: Are you a student or alum who’s always thought about getting involved in our award-winning K-12 STEM Outreach program?

Perfect, because our next ECE MeetUp event on Jan. 14 goes out to you.

Our own Dr. Betty Lise Anderson discusses the program, teaches you how to build several outreach engineering projects, and then you can learn how to assist the program moving forward.

Find all the details, plus a word from ECE alumnus and MeetUp organizer Mark Morscher, at the link:



Electrical and Computer Engineering Colloquium – Tania Roy @ 260 Dreese Laboratory
Apr 4 @ 11:00 am – 12:00 pm

You are invited to a Dept. of Electrical and Computer Engineering Colloquium

Monday, April 4, 2016

11:30am-12:30pm  260 Dreese Lab

Dr. Tania Roy, UC Berkeley

Van der Waals Heterojunctions for Energy-Efficient Electronics

Two-dimensional materials show immense potential as successor to silicon for next generation electronics. Graphene, being semi-metallic, can be used as electrodes and interconnects and in transistors for analog applications. Hexagonal boron nitride is an insulator with a low dielectric constant. The versatile platform of transition metal dichalcogenides (TMDCs) offers semiconductors – with a range of bandgaps, also tunable with their number of layers, Mott insulators, semimetals, and superconductors. These materials, with surfaces free of native oxide and dangling bonds and precisely controllable thicknesses down to one atomic layer, exhibit excellent transport characteristics at regimes where conventional semiconductors would fail. These 2D materials can be stacked on one another seamlessly, without any lattice mismatch. The van der Waals (vdW) bonding leads to sharp interfaces without any interdiffusion of atoms. Thus, vdW heterojunctions can be used for a wide variety of applications, ranging from steep transistors, gate-tunable diodes, to non-volatile memory devices and tunable light emitting diodes.

In this talk, a vdW heterojunction-based all-two-dimensional transistor will be discussed. The all-2D transistor shows no surface roughness scattering, a property hitherto unforeseen in its three dimensional counterparts. A dual-gated MoS2/WSe2 vdW heterojunction diode can be tuned to operate in various diode operation regimes. The same device operates as a forward rectifying diode as well as a tunnel diode, merely by application of gate voltage. The first observation of gate controlled band to band tunneling in semiconducting 2D heterostructures was made here, enhancing the prospects of using vdW heterojunctions for low power electronic applications. A 2D/2D tunnel field effect transistor with WSe2 and SnSe2 will be discussed. VdW heterojunctions with graphene/h-BN/graphene show negative differential resistance, which can be used in analog applications, such as in oscillators and amplifiers. Also, a graphene/insulator/graphene heterostructure demonstrates resistive switching and can be used to make ultra-low power resistive memories. Thus, vdW heterojunctions display a new paradigm of materials innovation to sustain the aggressive improvement of electronics for the continued betterment of human lives.


Tania Roy received B.E. (Hons.) in Electrical and Electronics Engineering from B.I.T.S. Pilani, India in 2006. She obtained her Ph.D degree in Electrical Engineering from Vanderbilt University, TN in December 2011, where she worked on the reliability of GaN/AlGaN high electron mobility transistors for high power and high frequency electronics. Following that, she worked as a postdoctoral fellow at Georgia Institute of Technology on graphene-based devices for low power applications till 2013. She joined University of California, Berkeley as a postdoc in 2014 where she has been working on  two dimensional materials for future generation electronics. She made the world’s first all-two-dimensional transistor, and reported the first gate controlled Esaki diode with van der Waals heterojunctions. Her research interests include using novel functional materials for energy-efficient electronics.

SAVE THE DATE: April 16, Electrical and Computer Engineering Open House @ 205 Dreese Labs
Apr 16 @ 10:45 am – 1:00 pm

SAVE THE DATE: April 16, ECE Open House

Event for incoming 2016 ECE students
Saturday, April 16, 2016, 10:45 am to 1:00 pm

Welcome to The Ohio State University, future engineers, we’re honored you identified Electrical and Computer Engineering as your future major, or perhaps you remain undecided, hoping to learn more about what our program has to offer. In either case, you and your family are cordially invited to the:

Ohio State Department of Electrical and Computer Engineering 2016 Open House Tailgate – Saturday April 16, from 10 a.m. to 1:00 p.m. 

The Annual Open House introduces our most promising incoming freshmen to their futures in the Department of Electrical and Computer Engineering (ECE). We are holding the Open House with a tailgate theme to coincide with the Ohio State Buckeye’s Spring Football Game that afternoon. Food will be available in the Dreese lobby after the tours.
The ECE Open House Tailgate includes an overview of our program, laboratory tours, research displays, student organization displays, plus the opportunity to speak with and ask questions of some of our faculty, advisors and students. Witness the popular High Voltage Lab indoor “lightning display” and Tesla coil. Explore what Buckeye Bullet and Buckeye Current electric racing teams are about. We’ll even have faculty on-hand to show off displays in photonics, robotics and intelligent transportation.
As your freshmen year draws near, you may have questions about our program and the classes offered. Perhaps you are curious about the diverse doors of professional opportunities an ECE major can provide. Or, maybe you are simply eager to get a first-hand look at our classrooms, laboratories and research. ECE offers the broadest engineering educational route, playing a major role in all aspects of technology – including energy, computers, medicine, telecommunications, robotics, electronics, sensors, nanotechnology, networking, manufacturing, automotive, multimedia and even aerospace.
Invited Attendees RSVP online by Thursday, March 31 here:
Warning: In the event we have a huge RSVP response, we may have to limit attendees to the first 150. We look forward to meeting you and your family on Saturday, April 16.



Department of Electrical and Computer Engineering – John D. and Alice Nelson Kraus Memorial Student Poster Competition and MeetUp Event @ ElectroScience Laboratory
Apr 21 @ 6:00 pm – 7:00 pm

John D. and Alice Nelson Kraus Memorial Student Poster Competition and MeetUp Event

Thursday, April 21, 2016, 6:00 pm

The Ohio State University Alumni Association has asked Alumni to volunteer in April in association with the “Buckeyes Give: Month of Service” initiative. Given how much members of this group have benefited from the Department of Electrical and Computer Engineering through our educational experience and career opportunities, and more recently by opening their doors to us through Meetup events, I think it is appropriate to assist the Department as part of this call to action.

While there are ways to contribute overall to the Department goals through donations (, another way to pay forward is to assist in Department activities by volunteering and offering our experience and expertise. This next Meetup provides the opportunity to do this related to assisting Graduate students within the Department.

The John D. and Alice Nelson Kraus Memorial Student Poster Competition is an annual event where a select number of ECE Graduate Students present their research activities and findings.  Faculty and Alumni will interact with the students to learn about their research, provide feedback and judge the entries and presentation skills of the students.  This is a great opportunity to get a close-up look at the research ECE Graduate Students are performing and providing feedback regarding how they present their work.  On top of that, our input will directly determine the results of the competition.

You can read about last year’s event here:

There will not be a traditional “Meetup” agenda for this event.  Just show up during the time noted, register as a judge, and start to mingle with the students, faculty and Alumni.  Based on last year’s event, the Graduate students really appreciated and benefited from the Alumni participation!

Business casual dress is requested, and there will be refreshments provided.  Parking is free at the ESL.

– Mark Morscher, ECE alumnus and MeetUp organizer


ECE Seminar- Prof. Betty Lise Anderson @ 113 Dreese Lab
Sep 7 @ 5:15 pm – 6:15 pm

Secrets to a Terrific Technical Talk

Brought to you by Prof. Betty Lise Anderson of the Ohio State University Department of Electrical and Computer Engineering
Wednesday, September 7, 2016, 5:15 pm

If there were ever a more able educator to help explain how to make the technical both empowering and exciting, that person would be tour-de-force professor Betty Lise Anderson of The Ohio State University Department of Electrical and Computer Engineering.

For more than 25 years, Anderson has made learning and speaking about engineering lively, entertaining and memorable across campus and Ohio.

Current Ohio State ECE students, and anyone else curious to learn how to advance their presentation skills, can now take advantage of her advice. In past years the presentation has earned large crowds, so get there early.

“It doesn’t take acting skills or stage presence to give a good technical talk, but it does take some planning. It’s not the same as writing a paper! We offer some strategies for organizing your talk so that people can grasp your awesome technical content without being scared away or put to sleep,” Anderson explains. “We’ll also go over how to make effective technical slides, and share some great stories from…unusual… presentations we have witnessed.”

The event is free and open to the public.

Date: Wednesday, Sept. 7

Time: 5:15 p.m. to 6:15 p.m.

Location: Rm. 113 Dreese Lab


ECE Seminar- Jin Wang @ E100 Scott Lab
Feb 9 @ 2:00 pm – 3:00 pm

When: 2 pm Thursday, Feb 9, 2017

Where: E100 Scott Laboratory

Title: How to Change the Landscape of Power Electronics with Wide Bandgap Power Devices

Speaker: Prof. Jin Wang, ECE Department, Ohio State University

Biography: Jin Wang received a B.S. degree from Xi’an Jiaotong University, in 1998, an M.S. degree from Wuhan University, in 2001, and a Ph.D. from Michigan State University, East Lansing, in 2005, all in electrical engineering.

From Sept., 2005 to Aug. 2007, he worked at the Ford Motor Company as a Core Power Electronics Engineer and contributed to the traction drive design of the Ford Fusion Hybrid.  He joined the Department of Electrical and Computer Engineering at The Ohio State University as an assistant professor in September 2007 and was promoted to associate professor in September 2013.  His research interests include wide bandgap power devices and their applications, high-voltage and high-power converter/inverters, integration of renewable energy sources, and electrification of transportation.

Dr. Wang received multiple teaching and research awards including the IEEE Power Electronics Society Richard M. Bass Young Engineer Award and the National Science Foundation’s CAREER Award, both in 2011; Ralph L. Boyer Award for Excellence in Undergraduate Teaching Innovation from the College of Engineering at The Ohio State University in 2012, and the Lumley Research Award of the College of Engineering at The Ohio State University in 2013.  Dr. Wang has over 100 peer-reviewed journal and conference publications and three patents.  Dr. Wang had been an Associate Editor for IEEE Transactions on Industry Applications from 2008 to 2014.  He initiated and served as the General Chair for the 1st IEEE Workshop on Wide Bandgap Power Devices and Applications in 2013.  Currently, Dr. Wang serves as an Associate Editor for IEEE Transactions on Power Electronics and IEEE Journal of Emerging and Selected Topics in Power Electronics (J-ESTPE).

ECE Seminar- Joe C. Campbell, University of Virginia @ 260 Dreese Laboratory
Apr 20 @ 1:00 pm – 2:00 pm
Title: High-Sensitivity Avalanche Photodiodes
Speaker: Joe C. Campbell, University of Virginia, Charlottesville, VA 22904
When: 1 pm, Thursday, April 20
Where: 260 Dreese Laboratory
Abstract: This talk will describe recent work on avalanche photodiodes including novel low-noise structures for telecommunications wavelengths and InAs APDs for mid-wave infrared. In the linear mode of operation, the internal gain of avalanche photodiodes (APDs) can provide higher sensitivity than p-i-n photodiodes, which is beneficial for many sensing applications. However, the origin of the APD gain is impact ionization, a stochastic process that results in excess noise and limits the gain-bandwidth. For the past four decades, reducing the excess noise factor, F(M), has been a focus of APD research and development. One structure that was proposed to achieve very low noise is the staircase APD in which avalanche events occur proximate to a sharp bandgap discontinuity, which function similarly to dynodes in a photomultiplier tube. We have recently demonstrated a staircase structure based on the AlxIn1-xAsySb1-y material system. In addition, we have used AlxIn1-xAsySb1-y to achieve low-noise avalanche gain using separate absorption and multiplication structures. These APDs have the potential to replace existing telecommunications detectors, which would have a transformative effect optical communications and data transmission. When biased above breakdown, APDs function as optical switches and can achieve single photon detection. This is referred to Geiger-mode operation. This talk will describe the performance and limitations of single photon avalanche diodes. 
Biography: Joe C. Campbell is the Lucian Carr Professor of Electrical and Computer Engineering at the University of Virginia in Charlottesville. Professor Campbell’s technical area is photodetectors. At present he is actively involved in single-photon-counting APDs, Si-based optoelectronics, high-speed low-noise avalanche photodiodes, high-power high-linearity photodiodes, and ultraviolet avalanche photodiodes. He has coauthored ten book chapters, 430 articles for refereed technical journals, and more than 400 conference presentations. Professor Campbell teaches graduate and undergraduate courses on lasers and optoelectronic components. In 2002 he was inducted into the National Academy of Engineering.
Host: Sanjay Krishna
ECE Distinguished Seminar Series – Jesus del Alamo, MIT @ Webinar
Jun 27 @ 4:45 pm – 5:45 pm

Webinar: Nanometer Scale III-V CMOS, sponsored by the IEEE EDS/Photonics Chapter Distinguished Lecturer Program


In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, transistors based on III-V compound semiconductors have emerged as a credible alternative. To get to this point, fundamental technical problems had to be solved though there are still many chal-lenges that need to be addressed before the first non-Si CMOS technology becomes a reality.  Among them, harnessing the out-standing electron transport properties of InGaAs, the leading n-channel material candidate, towards a high-performance na-noscale MOSFET has proven difficult; contact resistance, offstate characteristics, reliability and Si integration remain serious problems. Introducing a new material system is not the only challenge. Scalability to sub-10 nm gate dimensions also demands a new 3D transistor geometry. InGaAs FinFETs, Trigate MOSFETs and Nanowire MOSFETs have all been demonstrated but their performance is still disappointing.  To compound the challenge, a high-performance nanoscale p-type transistor is also re-quired.  Among III-Vs, InGaSb is the most promising candidate. Planar MOSFETs have been demonstrated but more advanced geometries remain elusive.  This talk will review recent progress as well as challenges confronting III-V electronics for future CMOS logic applications.


Jesús del Alamo is Director of the Microsystems Technology Laboratories, Donner Professor, and Professor of Electrical Engineering in the Department of Electrical Engineering and Computer Science at MIT. He holds degrees from Polytechnic University of Madrid (Telecommunications Engineer, 1980), and Stanford University (MS EE, 1983 and PhD EE, 1985). From 1977 to 1981 he was with the Institute of Solar Energy of the Polytechnic University of Madrid, investigating silicon photovoltaics. From 1981 to 1985, he carried out his PhD dissertation at Stanford University on minority car-rier transport in heavily doped silicon. From 1985 to 1988 he was research engineer with NTT LSI Laboratories in Atsugi (Japan) where he conducted research on III-V heterostructure field-effect transistors. He joined MIT in 1988.  From 1991 to 1996, Prof. del Alamo was an National Science Foundation Presidential Young Investigator. In 1999 he was elected a corresponding member of the Royal Spanish Academy of Engineering. In 2005, he was elected a Fellow of the IEEE and in 2014 he was elected a Fellow of the American Physical Society. Among other activities, Prof. del Alamo was Editor of IEEE Electron Device Letters from 2005 to 2014 and since 2013 he is the Director of the Microsystems Technology Laboratories at MIT.

Event hosted by: ECE Professor, Paul Berger